1. Field of the Invention
The present invention concerns an internal reference clock for Universal Serial Bus (“USB”) devices, and more particularly, concerns generating the reference clock making use of an integrated, free running oscillator metered by downstream received USB signals D+ and D− sent by a USB host or hub.
2. Related Art
USB devices need an accurate clock for reasons described hereafter. When a host or hub sends downstream data to a USB device there is a need at the device end to sample this data stream to recognize the logical states of the data, i.e. “1's” and “0's”. For the sample to occur periodically at the proper pace, the sampling clock must have a frequency similar to the one timing the downstream traffic in the host or hub.
Likewise, when the device sends upstream data on the bus, there is a need, at the host or hub end, to sample this data stream to recognize “1's” and “0's”. For the sample to occur periodically at the proper pace, the sampling clock must have a frequency similar to the one timing the upstream traffic in the device.
In the prior art, the host or hub and the device clock frequencies are similar since both the device and the host or hub have clocks based on quartz crystal or piezo resonator.
Further to the above-described clock similarity there is a need for the sampling to occur in the middle of a received bit cell. The sampling of a differential receiver output needs to occur in the middle of the bit cell, where the differential receiver output is giving a stable state. To fulfill this last requirement, the two above-mentioned clocks need to be phase locked. Synchronization patterns in the header of each message in both upstream and downstream directions, allow the phase locking of the device clock to the host's or hub's clock and vice versa. In complement to the Synchronization Pattern (“SP”) headers, a bit stuffing technique coupled with Non Return To Zero (“NRZI”) encoding guaranties certain transitions in the data streams used to synchronize the receiving clock. That is, at least, one transition is guaranteed to occur every seven bits at the receiver end.
To summarize, a Full Speed (“FS”) device clock needs to sample received data or drive transmittal data at an average rate of 12 Mbit per second ±0.25% while synchronized to the host or hub clock, and vice versa.
In an upstream situation, where the device sends data to the host or hub, not only must the average rate be accurate but also the jitter characteristics of the data stream for consecutive transitions must be better than ±3.5 ns, and for paired transitions better than ±4 ns.
Quartz crystal or piezo resonator based clock generators have conventionally been used to provide both the high level of accuracy of the average rate and the small jitters.
A USB device receives and sends data on a “USB” bus, i.e., a bus that meets requirements of the USB2.0 Specification with or without the On-The-Go supplement (“OTG”), comprising VBUS, GND, D+ and D−. A USB device has typically at least one printed circuit board (“PCB”) with at least one integrated circuit (“IC”) with pins connected to one or more other components onto the PCB. USB devices configured in this manner include for example, mass storage devices, some employing flash memory technology and others employing compact disk technology, printer devices or camera devices.
In those USB devices, at least one pin of an IC is used to connect the quartz crystal or piezo resonator located on the PCB externally to the IC. In many such devices the extra pins dedicated to connecting the quartz crystal or piezo resonator to the IC are a relatively small proportion of the IC's overall pins, and the quartz crystal or the piezo resonator occupies a relatively small portion of the overall PCB area. Consequently, in those devices, a quartz crystal or piezo resonator is compatible with their overall architecture.
Referring to FIG. 1, aspects of a prior art arrangement using a reference clock generator 130 driven by a quartz crystal or piezo resonator 150 are illustrated. According to this arrangement, a USB device 110 includes at least one silicon block 120 with integrated circuitry for a serial engine, transceivers and data stream manager to receive downstream signals and send upstream signals on a USB's D+ and D− lines and to manage data links to and from a function 140.
The USB device 110 brings to the user function 140 such as mass storage devices, printer device or camera device mentioned before. The device 110 is powered by VBUS when bus-powered, or by an external power supply when self-powered. FIG. 1 represents a bus-powered device 110 in a generalized fashion without depicting any specific function 140.
For a device 110 bringing a function compatible with IC technologies, such as memory, computing resources, cryptography or file management, function 140 may be merged into a single silicon block. The reference clock generator 130 delivers a clock to the silicon block 120. The reference clock generator 130 contains at least one IC associated with the quartz crystal or the piezo resonator to generate an electrical signal serving the silicon block 120 clock needs. There is an enable signal line between the silicon block 120 and the reference clock generator 130 used to start or stop the reference clock generator. This enables the silicon block 120 to start the clock when needed and stop it when not needed particularly to reduce the overall power consumption.
FIG. 2 represents aspects of another prior art arrangement for a device 210 where a quartz crystal or piezo resonator 250 is connected to a silicon block 220. As in FIG. 1, the silicon block 220 of FIG. 2 receives downstream signals and transmits upstream signals on a USB's D+ and D− lines as well as manages data streams from and to a function 240. However, in the device 210 of FIG. 2, the clock generator is included with the serial engine, transceivers, and data streams manager integrated circuitry on a single silicon block 220. The function 240 may likewise be merged onto silicon block 220.
Due to a number of issues including power consumption, size, and packaging limitations, the prior art USB devices 110 and 120 of FIGS. 1 and 2 are problematic for certain applications. These applications include a new family of USB devices, removable secure content (“RSC”) devices, connected directly to a Personal Computer (“PC”) USB port, or any enabled USB host such as OTG dual role device or Set Top Boxes through a simple pass through connector with possibly decoupling capacitors and inrush current limiting series resistor.
These RSC devices enable a new range of applications such as user authentication, platform Log On, Public Key Infrastructure, and also Digital Right Management for Voice Over the Internet Protocol (VOIP), cable TV, Digital Subscriber Line (DSL), where there is a need for data streaming while deciphering, or data storage for medical and other personal information such as banking account. Those devices have the Token form factor or preferably the Smart Card form factor, form factors, which are well known.
One such RSC device is the USB smart card also known as the USB Integrated Chip Card (“USB-ICC”), mechanical specifications for which are set out in the ISO 7816-2 specification, which is hereby incorporated herein by reference. By design USB-ICC's have only eight external contacts to which pins of a single IC are interconnected. Four of the USB-ICC's external contacts, C1, C4, C5 and C8, are used to connect respectively VBUS, D+, GND and D−. A quartz crystal or a piezo resonator cannot be connected to the IC of a USB-ICC within a required card thickness of less than 850 μm.
Moreover, USB-ICC and other USB RSC devices have to be power consumption conscious, since they can be connected to battery powered USB hosts such as laptop computers, mobile phones and Personal Digital Assistants. The latter two devices may be dual-role OTG devices with limited current availability for bus-powered devices. For example, in these applications power consumption is limited to less than few hundreds of microamperes for operation while in suspend state.
A RSC device will be preferably implemented making use of a single chip to be embedded into a Smart Card or a Subscriber Identification Module (SIM), which will enable massive diffusion. All plastic credit card and Digital Right Management (DRM) cards could be equipped with such a chip in a near future.
One application, in the WiFi or 802.11 context, could be for the removable secure content device to secure transactions as well as serving as a SIM. When used on a mobile platform, the power consumption performance is of prime importance.
There are known designs that address some of the limitations of the conventional USB devices 110 and 120 of FIGS. 1 and 2. Leydier et al., U.S. Pat. No. 6,343,364, “Method and device for local clock generation using universal serial bus downstream received signals DP and DM,” Jan. 29, 2002, (“Leydier, et al.”) discloses one such design and is hereby incorporated herein by reference.
Leydier, et al. disclose the use of USB downstream signals on D+ and D− to generate a clock on a single IC used for receiving and transmitting data without a quartz crystal or a piezo resonator and Leydier, et al. further disclose a method and a device for recovering the clock from the signals D+ and D− sent by a host or a hub in the context of a USB Low-Speed (“LS”) device. The disclosed method and device are implemented in an IC to generate a clock in a USB-ICC or a RSC device working in LS.
The teachings of Leydier, et al. also have applications for a FS USB-ICC or other such RSC devices. However, compared to LS operation, the USB specification and OTG supplement impose increased accuracy requirements of the average data rate and jitter characteristics for a device operating in USB FS mode. For this reason, and due to differences in specified communication patterns for LS and FS modes, a need exists for further improvements in clock recovery with reference to signals on D+ and D− sent by a host or a hub.
Bruhnke, International Publication No. WO 02/17047 A2, International Patent Filing No. PCT/DE01/03187, “Clock generator, in particular, for USB devices,” Publication Date Feb. 28, 2002 (“Bruhnke”), discloses another way for a USB device without a quartz crystal to recover a clock from signals received from a host or a hub.
The method disclosed by Bruhnke removes extra pulses from a local clock in order to produce a stabilized stream of pulses. Specifically, at Bruhnke, page 6, starting at line 15, it is described that each thirty-fourth pulse is removed from the clock 12. The resulting number of pulses matches the theoretical number of pulses per millisecond (“ms”), in terms of an average data rate per ms, but for almost all the pulses in the stabilized pulse stream the pace from pulse-to-pulse is faster than the required average data rate by more than the permissible error of ±0.25%. Therefore, the technique disclosed by Bruhnke, to selectively remove extra clock pulses, is problematic regarding jitter performances.
Based on the above brief explanation, it should be appreciated that a need exists for further improvements in generating a reference clock making use of an integrated, free running oscillator metered by downstream received USB signals sent by a host or hub.